Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16/] - Rev 246


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7206d 03h /ethmac/tags/rel_16/
245 Rev 1.7. mohor 7206d 20h /ethmac/tags/rel_16/
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7206d 22h /ethmac/tags/rel_16/
243 Late collision is not reported any more. tadejm 7207d 04h /ethmac/tags/rel_16/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7207d 19h /ethmac/tags/rel_16/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7207d 19h /ethmac/tags/rel_16/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7207d 19h /ethmac/tags/rel_16/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7207d 19h /ethmac/tags/rel_16/
238 Defines fixed to use generic RAM by default. mohor 7219d 23h /ethmac/tags/rel_16/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7222d 04h /ethmac/tags/rel_16/
235 rev 4. mohor 7222d 19h /ethmac/tags/rel_16/
234 Figure list assed to the revision 3. mohor 7223d 03h /ethmac/tags/rel_16/
233 Revision 0.3 released. Some figures added. mohor 7223d 03h /ethmac/tags/rel_16/
232 fpga define added. mohor 7227d 22h /ethmac/tags/rel_16/
231 Description of Core Modules added (figure). mohor 7229d 23h /ethmac/tags/rel_16/
229 case changed to casex. mohor 7233d 20h /ethmac/tags/rel_16/
227 Changed BIST scan signals. tadejm 7234d 00h /ethmac/tags/rel_16/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7234d 01h /ethmac/tags/rel_16/
225 Some minor changes. tadejm 7234d 02h /ethmac/tags/rel_16/
224 Signals for a wave window in Modelsim. tadejm 7234d 03h /ethmac/tags/rel_16/
223 Some code changed due to bug fixes. tadejm 7234d 03h /ethmac/tags/rel_16/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7238d 01h /ethmac/tags/rel_16/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7241d 01h /ethmac/tags/rel_16/
218 Typo error fixed. (When using Bist) mohor 7241d 03h /ethmac/tags/rel_16/
217 Bist supported. mohor 7241d 03h /ethmac/tags/rel_16/
216 Bist signals added. mohor 7241d 04h /ethmac/tags/rel_16/
215 Bist supported. mohor 7241d 04h /ethmac/tags/rel_16/
214 Signals for WISHBONE B3 compliant interface added. mohor 7242d 00h /ethmac/tags/rel_16/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7242d 00h /ethmac/tags/rel_16/
212 Minor $display change. mohor 7242d 00h /ethmac/tags/rel_16/

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.