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[/] [ethmac/] [tags/] [rel_16/] [bench/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 5477d 15h /ethmac/tags/rel_16/bench/verilog/
335 New directory structure. root 5534d 20h /ethmac/tags/rel_16/bench/verilog/
282 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7763d 15h /ethmac/tags/rel_16/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7763d 15h /ethmac/tags/rel_16/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7764d 17h /ethmac/tags/rel_16/bench/verilog/
274 Backup version. Not fully working. tadejm 7772d 11h /ethmac/tags/rel_16/bench/verilog/
267 Full duplex control frames tested. mohor 7828d 14h /ethmac/tags/rel_16/bench/verilog/
266 Flow control test almost finished. mohor 7833d 13h /ethmac/tags/rel_16/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7834d 04h /ethmac/tags/rel_16/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7834d 17h /ethmac/tags/rel_16/bench/verilog/
254 Temp version. mohor 7836d 10h /ethmac/tags/rel_16/bench/verilog/
252 Just some updates. tadejm 7836d 13h /ethmac/tags/rel_16/bench/verilog/
243 Late collision is not reported any more. tadejm 7841d 17h /ethmac/tags/rel_16/bench/verilog/
227 Changed BIST scan signals. tadejm 7868d 13h /ethmac/tags/rel_16/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7868d 17h /ethmac/tags/rel_16/bench/verilog/
216 Bist signals added. mohor 7875d 17h /ethmac/tags/rel_16/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7877d 17h /ethmac/tags/rel_16/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7896d 16h /ethmac/tags/rel_16/bench/verilog/
192 Some additional reports added tadej 7898d 13h /ethmac/tags/rel_16/bench/verilog/
191 Bug repaired in eth_phy device tadej 7898d 13h /ethmac/tags/rel_16/bench/verilog/

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