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[/] [ethmac/] [tags/] [rel_16] - Rev 232

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Rev Log message Author Age Path
232 fpga define added. mohor 7856d 03h /ethmac/tags/rel_16
231 Description of Core Modules added (figure). mohor 7858d 04h /ethmac/tags/rel_16
229 case changed to casex. mohor 7862d 00h /ethmac/tags/rel_16
227 Changed BIST scan signals. tadejm 7862d 04h /ethmac/tags/rel_16
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7862d 06h /ethmac/tags/rel_16
225 Some minor changes. tadejm 7862d 06h /ethmac/tags/rel_16
224 Signals for a wave window in Modelsim. tadejm 7862d 07h /ethmac/tags/rel_16
223 Some code changed due to bug fixes. tadejm 7862d 07h /ethmac/tags/rel_16
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7866d 05h /ethmac/tags/rel_16
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7869d 06h /ethmac/tags/rel_16
218 Typo error fixed. (When using Bist) mohor 7869d 08h /ethmac/tags/rel_16
217 Bist supported. mohor 7869d 08h /ethmac/tags/rel_16
216 Bist signals added. mohor 7869d 08h /ethmac/tags/rel_16
215 Bist supported. mohor 7869d 09h /ethmac/tags/rel_16
214 Signals for WISHBONE B3 compliant interface added. mohor 7870d 05h /ethmac/tags/rel_16
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7870d 05h /ethmac/tags/rel_16
212 Minor $display change. mohor 7870d 05h /ethmac/tags/rel_16
211 Bist added. mohor 7870d 05h /ethmac/tags/rel_16
210 BIST added. mohor 7870d 05h /ethmac/tags/rel_16
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7871d 08h /ethmac/tags/rel_16

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