OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16] - Rev 232

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
232 fpga define added. mohor 7870d 06h /ethmac/tags/rel_16
231 Description of Core Modules added (figure). mohor 7872d 08h /ethmac/tags/rel_16
229 case changed to casex. mohor 7876d 04h /ethmac/tags/rel_16
227 Changed BIST scan signals. tadejm 7876d 08h /ethmac/tags/rel_16
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7876d 09h /ethmac/tags/rel_16
225 Some minor changes. tadejm 7876d 10h /ethmac/tags/rel_16
224 Signals for a wave window in Modelsim. tadejm 7876d 11h /ethmac/tags/rel_16
223 Some code changed due to bug fixes. tadejm 7876d 11h /ethmac/tags/rel_16
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7880d 09h /ethmac/tags/rel_16
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7883d 10h /ethmac/tags/rel_16
218 Typo error fixed. (When using Bist) mohor 7883d 12h /ethmac/tags/rel_16
217 Bist supported. mohor 7883d 12h /ethmac/tags/rel_16
216 Bist signals added. mohor 7883d 12h /ethmac/tags/rel_16
215 Bist supported. mohor 7883d 12h /ethmac/tags/rel_16
214 Signals for WISHBONE B3 compliant interface added. mohor 7884d 08h /ethmac/tags/rel_16
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7884d 08h /ethmac/tags/rel_16
212 Minor $display change. mohor 7884d 08h /ethmac/tags/rel_16
211 Bist added. mohor 7884d 09h /ethmac/tags/rel_16
210 BIST added. mohor 7884d 09h /ethmac/tags/rel_16
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7885d 12h /ethmac/tags/rel_16
208 Virtual Silicon RAMs moved to lib directory tadej 7901d 06h /ethmac/tags/rel_16
207 Virtual Silicon RAM support fixed tadej 7901d 06h /ethmac/tags/rel_16
206 Virtual Silicon RAM added to the simulation. mohor 7901d 06h /ethmac/tags/rel_16
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7901d 07h /ethmac/tags/rel_16
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7901d 07h /ethmac/tags/rel_16
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7901d 07h /ethmac/tags/rel_16
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7904d 08h /ethmac/tags/rel_16
201 Core size added to the document. mohor 7904d 09h /ethmac/tags/rel_16
200 File with lower case checked in instead. mohor 7904d 09h /ethmac/tags/rel_16
199 Datasheet name changed to lower case name. mohor 7904d 09h /ethmac/tags/rel_16

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.