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Rev Log message Author Age Path
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7870d 20h /ethmac/tags/rel_17/
225 Some minor changes. tadejm 7870d 20h /ethmac/tags/rel_17/
224 Signals for a wave window in Modelsim. tadejm 7870d 22h /ethmac/tags/rel_17/
223 Some code changed due to bug fixes. tadejm 7870d 22h /ethmac/tags/rel_17/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7874d 20h /ethmac/tags/rel_17/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7877d 20h /ethmac/tags/rel_17/
218 Typo error fixed. (When using Bist) mohor 7877d 22h /ethmac/tags/rel_17/
217 Bist supported. mohor 7877d 22h /ethmac/tags/rel_17/
216 Bist signals added. mohor 7877d 22h /ethmac/tags/rel_17/
215 Bist supported. mohor 7877d 23h /ethmac/tags/rel_17/
214 Signals for WISHBONE B3 compliant interface added. mohor 7878d 19h /ethmac/tags/rel_17/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7878d 19h /ethmac/tags/rel_17/
212 Minor $display change. mohor 7878d 19h /ethmac/tags/rel_17/
211 Bist added. mohor 7878d 19h /ethmac/tags/rel_17/
210 BIST added. mohor 7878d 19h /ethmac/tags/rel_17/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7879d 23h /ethmac/tags/rel_17/
208 Virtual Silicon RAMs moved to lib directory tadej 7895d 16h /ethmac/tags/rel_17/
207 Virtual Silicon RAM support fixed tadej 7895d 17h /ethmac/tags/rel_17/
206 Virtual Silicon RAM added to the simulation. mohor 7895d 17h /ethmac/tags/rel_17/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7895d 17h /ethmac/tags/rel_17/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7895d 17h /ethmac/tags/rel_17/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7895d 17h /ethmac/tags/rel_17/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7898d 19h /ethmac/tags/rel_17/
201 Core size added to the document. mohor 7898d 19h /ethmac/tags/rel_17/
200 File with lower case checked in instead. mohor 7898d 19h /ethmac/tags/rel_17/
199 Datasheet name changed to lower case name. mohor 7898d 19h /ethmac/tags/rel_17/
198 Removed file. File with name in lower case will be added instead. mohor 7898d 19h /ethmac/tags/rel_17/
197 Ethernet Data Sheet. mohor 7898d 20h /ethmac/tags/rel_17/
196 Ethernet product brief. mohor 7898d 21h /ethmac/tags/rel_17/
195 Product brief removed because it is the same as Datasheet. mohor 7898d 21h /ethmac/tags/rel_17/

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