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Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7835d 00h /ethmac/tags/rel_17/
238 Defines fixed to use generic RAM by default. mohor 7847d 04h /ethmac/tags/rel_17/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7849d 09h /ethmac/tags/rel_17/
235 rev 4. mohor 7850d 00h /ethmac/tags/rel_17/
234 Figure list assed to the revision 3. mohor 7850d 08h /ethmac/tags/rel_17/
233 Revision 0.3 released. Some figures added. mohor 7850d 08h /ethmac/tags/rel_17/
232 fpga define added. mohor 7855d 03h /ethmac/tags/rel_17/
231 Description of Core Modules added (figure). mohor 7857d 04h /ethmac/tags/rel_17/
229 case changed to casex. mohor 7861d 01h /ethmac/tags/rel_17/
227 Changed BIST scan signals. tadejm 7861d 05h /ethmac/tags/rel_17/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7861d 06h /ethmac/tags/rel_17/
225 Some minor changes. tadejm 7861d 06h /ethmac/tags/rel_17/
224 Signals for a wave window in Modelsim. tadejm 7861d 08h /ethmac/tags/rel_17/
223 Some code changed due to bug fixes. tadejm 7861d 08h /ethmac/tags/rel_17/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7865d 06h /ethmac/tags/rel_17/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7868d 06h /ethmac/tags/rel_17/
218 Typo error fixed. (When using Bist) mohor 7868d 08h /ethmac/tags/rel_17/
217 Bist supported. mohor 7868d 08h /ethmac/tags/rel_17/
216 Bist signals added. mohor 7868d 08h /ethmac/tags/rel_17/
215 Bist supported. mohor 7868d 09h /ethmac/tags/rel_17/
214 Signals for WISHBONE B3 compliant interface added. mohor 7869d 05h /ethmac/tags/rel_17/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7869d 05h /ethmac/tags/rel_17/
212 Minor $display change. mohor 7869d 05h /ethmac/tags/rel_17/
211 Bist added. mohor 7869d 05h /ethmac/tags/rel_17/
210 BIST added. mohor 7869d 05h /ethmac/tags/rel_17/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7870d 09h /ethmac/tags/rel_17/
208 Virtual Silicon RAMs moved to lib directory tadej 7886d 03h /ethmac/tags/rel_17/
207 Virtual Silicon RAM support fixed tadej 7886d 03h /ethmac/tags/rel_17/
206 Virtual Silicon RAM added to the simulation. mohor 7886d 03h /ethmac/tags/rel_17/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7886d 04h /ethmac/tags/rel_17/

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