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[/] [ethmac/] [tags/] [rel_17/] - Rev 269

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269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7775d 07h /ethmac/tags/rel_17
268 Release 1.19. Control frame description changed. mohor 7829d 00h /ethmac/tags/rel_17
267 Full duplex control frames tested. mohor 7829d 02h /ethmac/tags/rel_17
266 Flow control test almost finished. mohor 7834d 01h /ethmac/tags/rel_17
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7834d 05h /ethmac/tags/rel_17
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7834d 16h /ethmac/tags/rel_17
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7834d 17h /ethmac/tags/rel_17
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7834d 17h /ethmac/tags/rel_17
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7835d 05h /ethmac/tags/rel_17
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7835d 18h /ethmac/tags/rel_17
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7835d 18h /ethmac/tags/rel_17
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7835d 18h /ethmac/tags/rel_17
255 TPauseRq synchronized to tx_clk. mohor 7835d 18h /ethmac/tags/rel_17
254 Temp version. mohor 7836d 22h /ethmac/tags/rel_17
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7837d 00h /ethmac/tags/rel_17
252 Just some updates. tadejm 7837d 01h /ethmac/tags/rel_17
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7837d 01h /ethmac/tags/rel_17
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7837d 01h /ethmac/tags/rel_17
248 wb_rst_i is used for MIIM reset. mohor 7838d 01h /ethmac/tags/rel_17
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7841d 04h /ethmac/tags/rel_17
245 Rev 1.7. mohor 7841d 22h /ethmac/tags/rel_17
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7842d 00h /ethmac/tags/rel_17
243 Late collision is not reported any more. tadejm 7842d 05h /ethmac/tags/rel_17
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7842d 20h /ethmac/tags/rel_17
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7842d 20h /ethmac/tags/rel_17
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7842d 20h /ethmac/tags/rel_17
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7842d 20h /ethmac/tags/rel_17
238 Defines fixed to use generic RAM by default. mohor 7855d 00h /ethmac/tags/rel_17
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7857d 06h /ethmac/tags/rel_17
235 rev 4. mohor 7857d 20h /ethmac/tags/rel_17

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