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Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8109d 00h /ethmac/tags/rel_17/
83 MAC address recognition was not correct (bytes swaped). mohor 8109d 00h /ethmac/tags/rel_17/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8109d 02h /ethmac/tags/rel_17/
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8109d 02h /ethmac/tags/rel_17/
80 Small fixes for external/internal DMA missmatches. mohor 8113d 04h /ethmac/tags/rel_17/
79 RetryCntLatched was unused and removed from design mohor 8113d 04h /ethmac/tags/rel_17/
78 WB_SEL_I was unused and removed from design mohor 8113d 04h /ethmac/tags/rel_17/
77 Interrupts changed mohor 8113d 04h /ethmac/tags/rel_17/
76 Interrupts changed in the top file mohor 8113d 04h /ethmac/tags/rel_17/
75 r_Bro is used for accepting/denying frames mohor 8113d 04h /ethmac/tags/rel_17/
74 Reset values are passed to registers through parameters mohor 8113d 05h /ethmac/tags/rel_17/
73 Number of interrupts changed mohor 8113d 05h /ethmac/tags/rel_17/
72 Retry is not activated when a Tx Underrun occured mohor 8117d 08h /ethmac/tags/rel_17/
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.		 mohor 8121d 09h /ethmac/tags/rel_17/
70 Small fixes. mohor 8121d 10h /ethmac/tags/rel_17/
69 Define missmatch fixed. mohor 8122d 07h /ethmac/tags/rel_17/
68 Registered trimmed. Unused registers removed. mohor 8123d 07h /ethmac/tags/rel_17/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8123d 08h /ethmac/tags/rel_17/
66 Testbench fixed, code simplified, unused signals removed. mohor 8123d 13h /ethmac/tags/rel_17/
65 Testbench fixed, code simplified, unused signals removed. mohor 8123d 14h /ethmac/tags/rel_17/

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