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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 202

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Rev	Log message	Author	Age	Path
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7930d 21h	/ethmac/tags/rel_17/rtl/verilog/
136	Parameter ResetValue changed to capital letters.	mohor	7931d 07h	/ethmac/tags/rel_17/rtl/verilog/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7933d 00h	/ethmac/tags/rel_17/rtl/verilog/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7933d 01h	/ethmac/tags/rel_17/rtl/verilog/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7933d 01h	/ethmac/tags/rel_17/rtl/verilog/
131	LinkFail signal was not latching appropriate bit.	mohor	7933d 01h	/ethmac/tags/rel_17/rtl/verilog/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7933d 02h	/ethmac/tags/rel_17/rtl/verilog/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7953d 01h	/ethmac/tags/rel_17/rtl/verilog/
126	InvalidSymbol generation changed.	mohor	7953d 01h	/ethmac/tags/rel_17/rtl/verilog/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7953d 01h	/ethmac/tags/rel_17/rtl/verilog/

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