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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 338


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338 root 4112d 15h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
335 New directory structure. root 4169d 20h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
287 This commit was manufactured by cvs2svn to create tag 'rel_17'. 6265d 18h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 6399d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 6407d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6408d 18h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6469d 04h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 6470d 06h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6471d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 6471d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 6472d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6476d 12h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6477d 08h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 6503d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 6510d 17h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 6511d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
210 BIST added. mohor 6511d 14h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6531d 13h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 6539d 16h /ethmac/tags/rel_17/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 6541d 20h /ethmac/tags/rel_17/rtl/verilog/eth_top.v

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