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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 164

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Rev	Log message	Author	Age	Path
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8118d 18h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
37	Link in the header changed.	mohor	8132d 22h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8181d 18h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8181d 22h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
23	Number of addresses (wb_adr_i) minimized.	mohor	8228d 21h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8229d 00h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8229d 20h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8253d 18h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8293d 18h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8302d 18h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v

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