Rev |
Log message |
Author |
Age |
Path |
210 |
BIST added. |
mohor |
7881d 05h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
202 |
CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated. |
mohor |
7901d 04h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
168 |
CarrierSenseLost bug fixed when operating in full duplex mode. |
mohor |
7909d 07h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
164 |
Ethernet debug registers removed. |
mohor |
7911d 11h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
161 |
Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set. |
mohor |
7912d 09h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
149 |
Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected. |
mohor |
7917d 03h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
125 |
RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted. |
mohor |
7958d 03h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
114 |
EXTERNAL_DMA removed. External DMA not supported. |
mohor |
7966d 03h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
106 |
Outputs registered. Reset changed for eth_wishbone module. |
mohor |
8041d 11h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
103 |
Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v |
mohor |
8052d 07h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
95 |
md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect. |
mohor |
8080d 08h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
80 |
Small fixes for external/internal DMA missmatches. |
mohor |
8107d 05h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
76 |
Interrupts changed in the top file |
mohor |
8107d 05h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
70 |
Small fixes. |
mohor |
8115d 11h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
68 |
Registered trimmed. Unused registers removed. |
mohor |
8117d 08h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
67 |
EXTERNAL_DMA used instead of WISHBONE_DMA. |
mohor |
8117d 08h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
65 |
Testbench fixed, code simplified, unused signals removed. |
mohor |
8117d 14h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
63 |
RxAbort is connected differently. |
mohor |
8118d 08h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
59 |
Changes that were lost when updating from 1.11 to 1.14 fixed. |
mohor |
8118d 10h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
52 |
Modified for Address Checking,
addition of eth_addrcheck.v |
billditt |
8119d 01h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
47 |
HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits. |
mohor |
8121d 05h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
43 |
Tx status is written back to the BD. |
mohor |
8122d 12h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
42 |
Rx status is written back to the BD. |
mohor |
8125d 05h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
41 |
non-DMA host interface added. Select the right configutation in eth_defines. |
mohor |
8127d 07h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
37 |
Link in the header changed. |
mohor |
8141d 11h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
34 |
RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors). |
mohor |
8190d 07h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
33 |
ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
mohor |
8190d 11h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
23 |
Number of addresses (wb_adr_i) minimized. |
mohor |
8237d 10h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
22 |
eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project. |
mohor |
8237d 13h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |
21 |
Status signals changed, Adress decoding changed, interrupt controller
added. |
mohor |
8238d 09h |
/ethmac/tags/rel_17/rtl/verilog/eth_top.v |