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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Rev 214

Rev	Log message	Author	Age	Path
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8111d 02h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8113d 05h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
43	Tx status is written back to the BD.	mohor	8114d 13h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
42	Rx status is written back to the BD.	mohor	8117d 06h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8119d 08h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
37	Link in the header changed.	mohor	8133d 12h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8182d 07h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8182d 11h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
23	Number of addresses (wb_adr_i) minimized.	mohor	8229d 11h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8229d 13h	/ethmac/tags/rel_17/rtl/verilog/eth_top.v