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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7969d 00h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7971d 03h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7974d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7976d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7983d 15h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7984d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7984d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7984d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8052d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8061d 09h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8087d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8091d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8097d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8097d 06h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8107d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8107d 04h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8108d 11h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8113d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8118d 01h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8118d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v

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