OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 166

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7900d 11h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7900d 14h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7902d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7906d 06h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7927d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7947d 06h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7949d 09h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7953d 00h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7954d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7961d 21h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7962d 11h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7963d 00h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7963d 04h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8030d 14h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8039d 15h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8065d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8069d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8075d 12h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8075d 12h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8085d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.