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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 166

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166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7914d 12h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7914d 15h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7916d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7920d 07h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7941d 07h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7961d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7963d 11h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7967d 01h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7968d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7975d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7976d 13h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7977d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7977d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8044d 16h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8053d 17h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8079d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8083d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8089d 13h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8089d 13h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8099d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8099d 12h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8100d 19h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8106d 07h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8110d 09h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8110d 10h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8121d 09h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8121d 14h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8121d 14h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8122d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8124d 09h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v

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