URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 270

Rev	Log message	Author	Age	Path
118	ShiftEnded synchronization changed.	mohor	7974d 13h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7975d 22h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7983d 11h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7984d 01h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7984d 14h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7984d 17h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8052d 04h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8061d 05h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8086d 22h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8090d 22h	/ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v