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Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 7901d 20h /ethmac/tags/rel_18/
179 Beautiful tests merget together mohor 7901d 21h /ethmac/tags/rel_18/
178 Rearanged testcases mohor 7901d 21h /ethmac/tags/rel_18/
177 Bug in MIIM fixed. mohor 7902d 01h /ethmac/tags/rel_18/
176 lists changed to new directory structure mohor 7902d 02h /ethmac/tags/rel_18/
175 Script fixed to new dir structure mohor 7902d 02h /ethmac/tags/rel_18/
174 Directory keeper mohor 7902d 02h /ethmac/tags/rel_18/
173 Keeps the directory mohor 7902d 02h /ethmac/tags/rel_18/
172 NCSIM simulation environment added to cvs mohor 7902d 02h /ethmac/tags/rel_18/
171 NCSIM simulation environment added. mohor 7902d 03h /ethmac/tags/rel_18/
170 Headers changed. mohor 7902d 03h /ethmac/tags/rel_18/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7902d 04h /ethmac/tags/rel_18/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7903d 01h /ethmac/tags/rel_18/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7904d 01h /ethmac/tags/rel_18/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7905d 02h /ethmac/tags/rel_18/
165 HASH improvement needed. mohor 7905d 05h /ethmac/tags/rel_18/
164 Ethernet debug registers removed. mohor 7905d 05h /ethmac/tags/rel_18/
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7905d 21h /ethmac/tags/rel_18/
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7905d 21h /ethmac/tags/rel_18/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7906d 02h /ethmac/tags/rel_18/

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