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[/] [ethmac/] [tags/] [rel_18/] - Rev 216

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216 Bist signals added. mohor 7872d 06h /ethmac/tags/rel_18
215 Bist supported. mohor 7872d 07h /ethmac/tags/rel_18
214 Signals for WISHBONE B3 compliant interface added. mohor 7873d 03h /ethmac/tags/rel_18
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7873d 03h /ethmac/tags/rel_18
212 Minor $display change. mohor 7873d 03h /ethmac/tags/rel_18
211 Bist added. mohor 7873d 03h /ethmac/tags/rel_18
210 BIST added. mohor 7873d 03h /ethmac/tags/rel_18
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7874d 06h /ethmac/tags/rel_18
208 Virtual Silicon RAMs moved to lib directory tadej 7890d 00h /ethmac/tags/rel_18
207 Virtual Silicon RAM support fixed tadej 7890d 00h /ethmac/tags/rel_18
206 Virtual Silicon RAM added to the simulation. mohor 7890d 01h /ethmac/tags/rel_18
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7890d 01h /ethmac/tags/rel_18
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7890d 01h /ethmac/tags/rel_18
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7890d 01h /ethmac/tags/rel_18
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7893d 02h /ethmac/tags/rel_18
201 Core size added to the document. mohor 7893d 03h /ethmac/tags/rel_18
200 File with lower case checked in instead. mohor 7893d 03h /ethmac/tags/rel_18
199 Datasheet name changed to lower case name. mohor 7893d 03h /ethmac/tags/rel_18
198 Removed file. File with name in lower case will be added instead. mohor 7893d 03h /ethmac/tags/rel_18
197 Ethernet Data Sheet. mohor 7893d 03h /ethmac/tags/rel_18

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