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Rev Log message Author Age Path
225 Some minor changes. tadejm 7868d 15h /ethmac/tags/rel_18/
224 Signals for a wave window in Modelsim. tadejm 7868d 16h /ethmac/tags/rel_18/
223 Some code changed due to bug fixes. tadejm 7868d 16h /ethmac/tags/rel_18/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7872d 14h /ethmac/tags/rel_18/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7875d 15h /ethmac/tags/rel_18/
218 Typo error fixed. (When using Bist) mohor 7875d 17h /ethmac/tags/rel_18/
217 Bist supported. mohor 7875d 17h /ethmac/tags/rel_18/
216 Bist signals added. mohor 7875d 17h /ethmac/tags/rel_18/
215 Bist supported. mohor 7875d 18h /ethmac/tags/rel_18/
214 Signals for WISHBONE B3 compliant interface added. mohor 7876d 14h /ethmac/tags/rel_18/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7876d 14h /ethmac/tags/rel_18/
212 Minor $display change. mohor 7876d 14h /ethmac/tags/rel_18/
211 Bist added. mohor 7876d 14h /ethmac/tags/rel_18/
210 BIST added. mohor 7876d 14h /ethmac/tags/rel_18/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7877d 17h /ethmac/tags/rel_18/
208 Virtual Silicon RAMs moved to lib directory tadej 7893d 11h /ethmac/tags/rel_18/
207 Virtual Silicon RAM support fixed tadej 7893d 11h /ethmac/tags/rel_18/
206 Virtual Silicon RAM added to the simulation. mohor 7893d 11h /ethmac/tags/rel_18/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7893d 12h /ethmac/tags/rel_18/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7893d 12h /ethmac/tags/rel_18/

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