OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_18/] - Rev 244

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7839d 16h /ethmac/tags/rel_18
243 Late collision is not reported any more. tadejm 7839d 22h /ethmac/tags/rel_18
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7840d 13h /ethmac/tags/rel_18
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7840d 13h /ethmac/tags/rel_18
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7840d 13h /ethmac/tags/rel_18
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7840d 13h /ethmac/tags/rel_18
238 Defines fixed to use generic RAM by default. mohor 7852d 17h /ethmac/tags/rel_18
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7854d 22h /ethmac/tags/rel_18
235 rev 4. mohor 7855d 13h /ethmac/tags/rel_18
234 Figure list assed to the revision 3. mohor 7855d 21h /ethmac/tags/rel_18
233 Revision 0.3 released. Some figures added. mohor 7855d 21h /ethmac/tags/rel_18
232 fpga define added. mohor 7860d 16h /ethmac/tags/rel_18
231 Description of Core Modules added (figure). mohor 7862d 17h /ethmac/tags/rel_18
229 case changed to casex. mohor 7866d 14h /ethmac/tags/rel_18
227 Changed BIST scan signals. tadejm 7866d 18h /ethmac/tags/rel_18
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7866d 19h /ethmac/tags/rel_18
225 Some minor changes. tadejm 7866d 19h /ethmac/tags/rel_18
224 Signals for a wave window in Modelsim. tadejm 7866d 21h /ethmac/tags/rel_18
223 Some code changed due to bug fixes. tadejm 7866d 21h /ethmac/tags/rel_18
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7870d 19h /ethmac/tags/rel_18

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.