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[/] [ethmac/] [tags/] [rel_18/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 350

Rev	Log message	Author	Age	Path
338		root	5477d 06h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
335	New directory structure.	root	5534d 11h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
289	This commit was manufactured by cvs2svn to create tag 'rel_18'.		7604d 06h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7868d 04h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7876d 05h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7893d 03h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7955d 05h	/ethmac/tags/rel_18/rtl/verilog/eth_spram_256x32.v