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Rev Log message Author Age Path
245 Rev 1.7. mohor 7855d 02h /ethmac/tags/rel_18
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7855d 04h /ethmac/tags/rel_18
243 Late collision is not reported any more. tadejm 7855d 09h /ethmac/tags/rel_18
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7856d 00h /ethmac/tags/rel_18
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7856d 00h /ethmac/tags/rel_18
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7856d 00h /ethmac/tags/rel_18
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7856d 00h /ethmac/tags/rel_18
238 Defines fixed to use generic RAM by default. mohor 7868d 04h /ethmac/tags/rel_18
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7870d 10h /ethmac/tags/rel_18
235 rev 4. mohor 7871d 00h /ethmac/tags/rel_18
234 Figure list assed to the revision 3. mohor 7871d 08h /ethmac/tags/rel_18
233 Revision 0.3 released. Some figures added. mohor 7871d 09h /ethmac/tags/rel_18
232 fpga define added. mohor 7876d 04h /ethmac/tags/rel_18
231 Description of Core Modules added (figure). mohor 7878d 05h /ethmac/tags/rel_18
229 case changed to casex. mohor 7882d 02h /ethmac/tags/rel_18
227 Changed BIST scan signals. tadejm 7882d 05h /ethmac/tags/rel_18
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7882d 07h /ethmac/tags/rel_18
225 Some minor changes. tadejm 7882d 07h /ethmac/tags/rel_18
224 Signals for a wave window in Modelsim. tadejm 7882d 08h /ethmac/tags/rel_18
223 Some code changed due to bug fixes. tadejm 7882d 08h /ethmac/tags/rel_18

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