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[/] [ethmac/] [tags/] [rel_19/] - Rev 21

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Rev	Log message	Author	Age	Path
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8238d 17h	/ethmac/tags/rel_19/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8262d 14h	/ethmac/tags/rel_19/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8262d 14h	/ethmac/tags/rel_19/
18	Few little NCSIM warnings fixed.	mohor	8275d 15h	/ethmac/tags/rel_19/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8302d 15h	/ethmac/tags/rel_19/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8309d 21h	/ethmac/tags/rel_19/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8311d 14h	/ethmac/tags/rel_19/
14	Unconnected signals are now connected.	mohor	8315d 20h	/ethmac/tags/rel_19/
13	New directory structure. Files upodated and put together.	mohor	8318d 04h	/ethmac/tags/rel_19/
12	Directory structure changed. Files checked and joind together.	mohor	8318d 07h	/ethmac/tags/rel_19/
11	Directory structure changed. Files checked and joind together.	mohor	8318d 08h	/ethmac/tags/rel_19/
10	Directory structure changed. Files checked and joind together.	mohor	8318d 08h	/ethmac/tags/rel_19/
9	Documentation updated to be synchronized to the verilog files.	mohor	8345d 16h	/ethmac/tags/rel_19/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8372d 21h	/ethmac/tags/rel_19/
7	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8372d 21h	/ethmac/tags/rel_19/
6	no message	mohor	8372d 21h	/ethmac/tags/rel_19/
5	This is a Microsoft version of the spec in the pdf format.	mohor	8377d 07h	/ethmac/tags/rel_19/
4	deleted	mohor	8377d 07h	/ethmac/tags/rel_19/
2	no message	mohor	8449d 07h	/ethmac/tags/rel_19/
1	Standard project directories initialized by cvs2svn.		8449d 07h	/ethmac/tags/rel_19/

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[/] [ethmac/] [tags/] [rel_19/] - Rev 21

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