OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 365

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5475d 05h /ethmac/tags/rel_19/bench/verilog/
335 New directory structure. root 5532d 10h /ethmac/tags/rel_19/bench/verilog/
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7567d 07h /ethmac/tags/rel_19/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7628d 09h /ethmac/tags/rel_19/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7761d 05h /ethmac/tags/rel_19/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7762d 07h /ethmac/tags/rel_19/bench/verilog/
274 Backup version. Not fully working. tadejm 7770d 01h /ethmac/tags/rel_19/bench/verilog/
267 Full duplex control frames tested. mohor 7826d 04h /ethmac/tags/rel_19/bench/verilog/
266 Flow control test almost finished. mohor 7831d 03h /ethmac/tags/rel_19/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7831d 18h /ethmac/tags/rel_19/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7832d 07h /ethmac/tags/rel_19/bench/verilog/
254 Temp version. mohor 7834d 00h /ethmac/tags/rel_19/bench/verilog/
252 Just some updates. tadejm 7834d 03h /ethmac/tags/rel_19/bench/verilog/
243 Late collision is not reported any more. tadejm 7839d 07h /ethmac/tags/rel_19/bench/verilog/
227 Changed BIST scan signals. tadejm 7866d 03h /ethmac/tags/rel_19/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7866d 07h /ethmac/tags/rel_19/bench/verilog/
216 Bist signals added. mohor 7873d 07h /ethmac/tags/rel_19/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7875d 07h /ethmac/tags/rel_19/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7894d 06h /ethmac/tags/rel_19/bench/verilog/
192 Some additional reports added tadej 7896d 03h /ethmac/tags/rel_19/bench/verilog/
191 Bug repaired in eth_phy device tadej 7896d 03h /ethmac/tags/rel_19/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7896d 04h /ethmac/tags/rel_19/bench/verilog/
188 PHY changed. tadej 7897d 00h /ethmac/tags/rel_19/bench/verilog/
182 Full duplex test improved. tadej 7898d 03h /ethmac/tags/rel_19/bench/verilog/
181 MIIM test look better. mohor 7898d 05h /ethmac/tags/rel_19/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7901d 01h /ethmac/tags/rel_19/bench/verilog/
179 Beautiful tests merget together mohor 7901d 02h /ethmac/tags/rel_19/bench/verilog/
178 Rearanged testcases mohor 7901d 02h /ethmac/tags/rel_19/bench/verilog/
177 Bug in MIIM fixed. mohor 7901d 06h /ethmac/tags/rel_19/bench/verilog/
170 Headers changed. mohor 7901d 08h /ethmac/tags/rel_19/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.