OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] - Rev 272

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7862d 11h /ethmac/tags/rel_19/rtl
232 fpga define added. mohor 7868d 05h /ethmac/tags/rel_19/rtl
229 case changed to casex. mohor 7874d 03h /ethmac/tags/rel_19/rtl
227 Changed BIST scan signals. tadejm 7874d 07h /ethmac/tags/rel_19/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7874d 08h /ethmac/tags/rel_19/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7878d 08h /ethmac/tags/rel_19/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7881d 08h /ethmac/tags/rel_19/rtl
218 Typo error fixed. (When using Bist) mohor 7881d 10h /ethmac/tags/rel_19/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7882d 07h /ethmac/tags/rel_19/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7882d 07h /ethmac/tags/rel_19/rtl

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.