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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 125

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Rev	Log message	Author	Age	Path
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7966d 11h	/ethmac/tags/rel_19/rtl/verilog/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7968d 12h	/ethmac/tags/rel_19/rtl/verilog/
120	Unused files removed.	mohor	7968d 13h	/ethmac/tags/rel_19/rtl/verilog/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7968d 13h	/ethmac/tags/rel_19/rtl/verilog/
118	ShiftEnded synchronization changed.	mohor	7972d 04h	/ethmac/tags/rel_19/rtl/verilog/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7973d 13h	/ethmac/tags/rel_19/rtl/verilog/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7974d 10h	/ethmac/tags/rel_19/rtl/verilog/
113	RxPointer bug fixed.	mohor	7981d 02h	/ethmac/tags/rel_19/rtl/verilog/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7981d 16h	/ethmac/tags/rel_19/rtl/verilog/
111	Master state machine had a bug when switching from master write to master read.	mohor	7982d 05h	/ethmac/tags/rel_19/rtl/verilog/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7982d 08h	/ethmac/tags/rel_19/rtl/verilog/
109	Comment removed.	mohor	7982d 09h	/ethmac/tags/rel_19/rtl/verilog/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8049d 19h	/ethmac/tags/rel_19/rtl/verilog/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8058d 20h	/ethmac/tags/rel_19/rtl/verilog/
104	FCS should not be included in NibbleMinFl.	mohor	8060d 14h	/ethmac/tags/rel_19/rtl/verilog/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8060d 15h	/ethmac/tags/rel_19/rtl/verilog/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8060d 15h	/ethmac/tags/rel_19/rtl/verilog/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8060d 15h	/ethmac/tags/rel_19/rtl/verilog/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8060d 15h	/ethmac/tags/rel_19/rtl/verilog/
97	Small typo fixed.	lampret	8084d 13h	/ethmac/tags/rel_19/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 125

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