URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 147

Rev	Log message	Author	Age	Path
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7966d 02h	/ethmac/tags/rel_19/rtl/verilog/
118	ShiftEnded synchronization changed.	mohor	7969d 17h	/ethmac/tags/rel_19/rtl/verilog/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7971d 02h	/ethmac/tags/rel_19/rtl/verilog/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7971d 23h	/ethmac/tags/rel_19/rtl/verilog/
113	RxPointer bug fixed.	mohor	7978d 15h	/ethmac/tags/rel_19/rtl/verilog/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7979d 05h	/ethmac/tags/rel_19/rtl/verilog/
111	Master state machine had a bug when switching from master write to master read.	mohor	7979d 18h	/ethmac/tags/rel_19/rtl/verilog/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7979d 21h	/ethmac/tags/rel_19/rtl/verilog/
109	Comment removed.	mohor	7979d 22h	/ethmac/tags/rel_19/rtl/verilog/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8047d 08h	/ethmac/tags/rel_19/rtl/verilog/