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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 244

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Rev	Log message	Author	Age	Path
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7838d 04h	/ethmac/tags/rel_19/rtl/verilog/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7839d 00h	/ethmac/tags/rel_19/rtl/verilog/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7839d 00h	/ethmac/tags/rel_19/rtl/verilog/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7839d 00h	/ethmac/tags/rel_19/rtl/verilog/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7839d 00h	/ethmac/tags/rel_19/rtl/verilog/
238	Defines fixed to use generic RAM by default.	mohor	7851d 04h	/ethmac/tags/rel_19/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7853d 10h	/ethmac/tags/rel_19/rtl/verilog/
232	fpga define added.	mohor	7859d 04h	/ethmac/tags/rel_19/rtl/verilog/
229	case changed to casex.	mohor	7865d 02h	/ethmac/tags/rel_19/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7865d 06h	/ethmac/tags/rel_19/rtl/verilog/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7865d 07h	/ethmac/tags/rel_19/rtl/verilog/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7869d 07h	/ethmac/tags/rel_19/rtl/verilog/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7872d 07h	/ethmac/tags/rel_19/rtl/verilog/
218	Typo error fixed. (When using Bist)	mohor	7872d 09h	/ethmac/tags/rel_19/rtl/verilog/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7873d 06h	/ethmac/tags/rel_19/rtl/verilog/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7873d 06h	/ethmac/tags/rel_19/rtl/verilog/
212	Minor $display change.	mohor	7873d 06h	/ethmac/tags/rel_19/rtl/verilog/
211	Bist added.	mohor	7873d 06h	/ethmac/tags/rel_19/rtl/verilog/
210	BIST added.	mohor	7873d 06h	/ethmac/tags/rel_19/rtl/verilog/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7890d 04h	/ethmac/tags/rel_19/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 244

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