OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_defines.v] - Rev 238

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7856d 01h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7864d 00h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7878d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
211 Bist added. mohor 7878d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7895d 01h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7914d 00h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7932d 21h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7935d 00h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7957d 04h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8038d 09h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8047d 10h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8083d 06h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 8104d 03h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 8114d 05h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8114d 06h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8115d 08h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8115d 23h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 8118d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 8122d 03h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8125d 02h /ethmac/tags/rel_19/rtl/verilog/eth_defines.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.