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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_registers.v] - Rev 338


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338 root 4112d 15h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
335 New directory structure. root 4169d 20h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 6204d 16h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 6321d 14h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6469d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6471d 12h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6476d 11h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 6541d 19h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 6547d 11h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 6563d 14h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 6566d 08h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 6566d 08h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6566d 08h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6568d 12h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6682d 16h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 6737d 14h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 6746d 17h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 6747d 16h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 6748d 19h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 6749d 10h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v

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