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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_registers.v] - Rev 164

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164 Ethernet debug registers removed. mohor 7904d 13h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7910d 05h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7926d 08h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7929d 01h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7929d 02h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7929d 02h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7931d 05h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8045d 10h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8100d 08h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8109d 11h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8110d 10h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8111d 13h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8112d 04h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8114d 07h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8134d 13h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8183d 09h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8183d 14h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8230d 15h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8231d 12h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8255d 09h /ethmac/tags/rel_19/rtl/verilog/eth_registers.v

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