URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] [eth_top.v] - Rev 240

Rev	Log message	Author	Age	Path
65	Testbench fixed, code simplified, unused signals removed.	mohor	8125d 23h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
63	RxAbort is connected differently.	mohor	8126d 17h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
59	Changes that were lost when updating from 1.11 to 1.14 fixed.	mohor	8126d 19h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8127d 10h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8129d 14h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
43	Tx status is written back to the BD.	mohor	8130d 21h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
42	Rx status is written back to the BD.	mohor	8133d 14h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8135d 17h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
37	Link in the header changed.	mohor	8149d 20h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8198d 16h	/ethmac/tags/rel_19/rtl/verilog/eth_top.v