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[/] [ethmac/] [tags/] [rel_2/] - Rev 117

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Rev Log message Author Age Path
117 Clock mrx_clk set to 2.5 MHz. mohor 6358d 07h /ethmac/tags/rel_2/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6358d 07h /ethmac/tags/rel_2/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6359d 04h /ethmac/tags/rel_2/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6360d 02h /ethmac/tags/rel_2/
113 RxPointer bug fixed. mohor 6366d 18h /ethmac/tags/rel_2/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6367d 07h /ethmac/tags/rel_2/
111 Master state machine had a bug when switching from master write to
master read.
mohor 6367d 21h /ethmac/tags/rel_2/
110 m_wb_cyc_o signal released after every single transfer. mohor 6368d 00h /ethmac/tags/rel_2/
109 Comment removed. mohor 6368d 00h /ethmac/tags/rel_2/
108 Testbench supports unaligned accesses. mohor 6435d 10h /ethmac/tags/rel_2/
107 TX_BUF_BASE changed. mohor 6435d 10h /ethmac/tags/rel_2/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6435d 10h /ethmac/tags/rel_2/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6444d 12h /ethmac/tags/rel_2/
104 FCS should not be included in NibbleMinFl. mohor 6446d 06h /ethmac/tags/rel_2/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6446d 06h /ethmac/tags/rel_2/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6446d 06h /ethmac/tags/rel_2/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6446d 07h /ethmac/tags/rel_2/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6446d 07h /ethmac/tags/rel_2/
99 Document revised. mohor 6453d 05h /ethmac/tags/rel_2/
98 Document revised. mohor 6453d 06h /ethmac/tags/rel_2/

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