URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 104

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
104	FCS should not be included in NibbleMinFl.	mohor	8044d 00h	/ethmac/tags/rel_2/rtl
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8044d 01h	/ethmac/tags/rel_2/rtl
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8044d 01h	/ethmac/tags/rel_2/rtl
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8044d 01h	/ethmac/tags/rel_2/rtl
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8044d 01h	/ethmac/tags/rel_2/rtl
97	Small typo fixed.	lampret	8067d 23h	/ethmac/tags/rel_2/rtl
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8071d 23h	/ethmac/tags/rel_2/rtl
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8072d 02h	/ethmac/tags/rel_2/rtl
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8072d 02h	/ethmac/tags/rel_2/rtl
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8077d 00h	/ethmac/tags/rel_2/rtl
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8078d 02h	/ethmac/tags/rel_2/rtl
91	Comments in Slovene language removed.	mohor	8078d 02h	/ethmac/tags/rel_2/rtl
90	casex changed with case, fifo reset changed.	mohor	8078d 02h	/ethmac/tags/rel_2/rtl
88	rx_fifo was not always cleared ok. Fixed.	mohor	8087d 23h	/ethmac/tags/rel_2/rtl
87	Status was not latched correctly sometimes. Fixed.	mohor	8088d 01h	/ethmac/tags/rel_2/rtl
86	Big Endian problem when sending frames fixed.	mohor	8089d 08h	/ethmac/tags/rel_2/rtl
85	Log info was missing.	mohor	8094d 18h	/ethmac/tags/rel_2/rtl
84	LinkFail signal was not latching appropriate bit.	mohor	8094d 18h	/ethmac/tags/rel_2/rtl
83	MAC address recognition was not correct (bytes swaped).	mohor	8094d 18h	/ethmac/tags/rel_2/rtl
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8094d 20h	/ethmac/tags/rel_2/rtl

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 104

Filtering Options