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[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 338

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Rev Log message Author Age Path
338 root 5690d 10h /ethmac/tags/rel_2/rtl/
335 New directory structure. root 5747d 16h /ethmac/tags/rel_2/rtl/
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8166d 07h /ethmac/tags/rel_2/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 8166d 07h /ethmac/tags/rel_2/rtl/
126 InvalidSymbol generation changed. mohor 8166d 07h /ethmac/tags/rel_2/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 8166d 07h /ethmac/tags/rel_2/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8168d 09h /ethmac/tags/rel_2/rtl/
120 Unused files removed. mohor 8168d 10h /ethmac/tags/rel_2/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8168d 10h /ethmac/tags/rel_2/rtl/
118 ShiftEnded synchronization changed. mohor 8172d 01h /ethmac/tags/rel_2/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8173d 09h /ethmac/tags/rel_2/rtl/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8174d 07h /ethmac/tags/rel_2/rtl/
113 RxPointer bug fixed. mohor 8180d 23h /ethmac/tags/rel_2/rtl/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8181d 12h /ethmac/tags/rel_2/rtl/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8182d 02h /ethmac/tags/rel_2/rtl/
110 m_wb_cyc_o signal released after every single transfer. mohor 8182d 05h /ethmac/tags/rel_2/rtl/
109 Comment removed. mohor 8182d 05h /ethmac/tags/rel_2/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8249d 15h /ethmac/tags/rel_2/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8258d 17h /ethmac/tags/rel_2/rtl/
104 FCS should not be included in NibbleMinFl. mohor 8260d 11h /ethmac/tags/rel_2/rtl/

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