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[/] [ethmac/] [tags/] [rel_2/] [rtl/] - Rev 338

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Rev Log message Author Age Path
338 root 5496d 08h /ethmac/tags/rel_2/rtl
335 New directory structure. root 5553d 14h /ethmac/tags/rel_2/rtl
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7972d 05h /ethmac/tags/rel_2/rtl
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7972d 05h /ethmac/tags/rel_2/rtl
126 InvalidSymbol generation changed. mohor 7972d 05h /ethmac/tags/rel_2/rtl
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7972d 05h /ethmac/tags/rel_2/rtl
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7974d 07h /ethmac/tags/rel_2/rtl
120 Unused files removed. mohor 7974d 08h /ethmac/tags/rel_2/rtl
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7974d 08h /ethmac/tags/rel_2/rtl
118 ShiftEnded synchronization changed. mohor 7977d 23h /ethmac/tags/rel_2/rtl
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7979d 08h /ethmac/tags/rel_2/rtl
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7980d 05h /ethmac/tags/rel_2/rtl
113 RxPointer bug fixed. mohor 7986d 21h /ethmac/tags/rel_2/rtl
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7987d 11h /ethmac/tags/rel_2/rtl
111 Master state machine had a bug when switching from master write to
master read.
mohor 7988d 00h /ethmac/tags/rel_2/rtl
110 m_wb_cyc_o signal released after every single transfer. mohor 7988d 03h /ethmac/tags/rel_2/rtl
109 Comment removed. mohor 7988d 04h /ethmac/tags/rel_2/rtl
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8055d 13h /ethmac/tags/rel_2/rtl
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8064d 15h /ethmac/tags/rel_2/rtl
104 FCS should not be included in NibbleMinFl. mohor 8066d 09h /ethmac/tags/rel_2/rtl

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