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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] - Rev 62

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Rev	Log message	Author	Age	Path
62	RxAbort is an output. No need to have is declared as wire.	mohor	8139d 06h	/ethmac/tags/rel_2/rtl/verilog/
61	RxStartFrm cleared when abort or retry comes.	mohor	8139d 08h	/ethmac/tags/rel_2/rtl/verilog/
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8139d 08h	/ethmac/tags/rel_2/rtl/verilog/
59	Changes that were lost when updating from 1.11 to 1.14 fixed.	mohor	8139d 09h	/ethmac/tags/rel_2/rtl/verilog/
58	File format changed.	mohor	8139d 09h	/ethmac/tags/rel_2/rtl/verilog/
57	Format of the file changed a bit.	mohor	8139d 09h	/ethmac/tags/rel_2/rtl/verilog/
56	File format fixed a bit.	mohor	8139d 09h	/ethmac/tags/rel_2/rtl/verilog/
55	Changed that were lost with last update put back to the file.	mohor	8139d 09h	/ethmac/tags/rel_2/rtl/verilog/
54	Addition of new module eth_addrcheck.v	billditt	8139d 23h	/ethmac/tags/rel_2/rtl/verilog/
53	Addition of new module eth_addrcheck.v	billditt	8139d 23h	/ethmac/tags/rel_2/rtl/verilog/
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8140d 00h	/ethmac/tags/rel_2/rtl/verilog/
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8140d 01h	/ethmac/tags/rel_2/rtl/verilog/
48	RxOverRun added to statuses.	mohor	8142d 03h	/ethmac/tags/rel_2/rtl/verilog/
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8142d 03h	/ethmac/tags/rel_2/rtl/verilog/
46	HASH0 and HASH1 registers added.	mohor	8142d 03h	/ethmac/tags/rel_2/rtl/verilog/
43	Tx status is written back to the BD.	mohor	8143d 11h	/ethmac/tags/rel_2/rtl/verilog/
42	Rx status is written back to the BD.	mohor	8146d 04h	/ethmac/tags/rel_2/rtl/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8148d 06h	/ethmac/tags/rel_2/rtl/verilog/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8149d 03h	/ethmac/tags/rel_2/rtl/verilog/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8153d 07h	/ethmac/tags/rel_2/rtl/verilog/

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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] - Rev 62

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