URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Rev	Log message	Author	Age	Path
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8123d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8127d 23h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8128d 00h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8138d 23h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8139d 04h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8139d 04h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8139d 19h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8141d 23h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8143d 07h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8146d 00h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v