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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 358

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Rev	Log message	Author	Age	Path
338		root	5470d 16h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5527d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
128	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7946d 13h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7946d 13h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7948d 16h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7952d 06h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7953d 15h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7961d 04h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7961d 18h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7962d 07h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7962d 10h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8029d 21h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8038d 22h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8064d 15h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8068d 15h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8074d 18h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8074d 18h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8084d 15h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8084d 17h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8086d 00h	/ethmac/tags/rel_2/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 358

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