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Rev Log message Author Age Path
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7954d 06h /ethmac/tags/rel_20/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7956d 07h /ethmac/tags/rel_20/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7956d 07h /ethmac/tags/rel_20/
120 Unused files removed. mohor 7956d 08h /ethmac/tags/rel_20/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7956d 08h /ethmac/tags/rel_20/
118 ShiftEnded synchronization changed. mohor 7959d 23h /ethmac/tags/rel_20/
117 Clock mrx_clk set to 2.5 MHz. mohor 7960d 09h /ethmac/tags/rel_20/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7960d 09h /ethmac/tags/rel_20/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7961d 07h /ethmac/tags/rel_20/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7962d 04h /ethmac/tags/rel_20/
113 RxPointer bug fixed. mohor 7968d 20h /ethmac/tags/rel_20/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7969d 10h /ethmac/tags/rel_20/
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7969d 23h /ethmac/tags/rel_20/
110 m_wb_cyc_o signal released after every single transfer. mohor 7970d 03h /ethmac/tags/rel_20/
109 Comment removed. mohor 7970d 03h /ethmac/tags/rel_20/
108 Testbench supports unaligned accesses. mohor 8037d 13h /ethmac/tags/rel_20/
107 TX_BUF_BASE changed. mohor 8037d 13h /ethmac/tags/rel_20/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8037d 13h /ethmac/tags/rel_20/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8046d 14h /ethmac/tags/rel_20/
104 FCS should not be included in NibbleMinFl. mohor 8048d 08h /ethmac/tags/rel_20/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8048d 09h /ethmac/tags/rel_20/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8048d 09h /ethmac/tags/rel_20/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8048d 09h /ethmac/tags/rel_20/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8048d 10h /ethmac/tags/rel_20/
99 Document revised. mohor 8055d 08h /ethmac/tags/rel_20/
98 Document revised. mohor 8055d 09h /ethmac/tags/rel_20/
97 Small typo fixed. lampret 8072d 07h /ethmac/tags/rel_20/
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8076d 07h /ethmac/tags/rel_20/
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8076d 10h /ethmac/tags/rel_20/
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8076d 10h /ethmac/tags/rel_20/

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