OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] - Rev 166

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7924d 21h /ethmac/tags/rel_20
165 HASH improvement needed. mohor 7925d 00h /ethmac/tags/rel_20
164 Ethernet debug registers removed. mohor 7925d 00h /ethmac/tags/rel_20
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7925d 16h /ethmac/tags/rel_20
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7925d 16h /ethmac/tags/rel_20
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7925d 21h /ethmac/tags/rel_20
160 error acknowledge cycle termination added to display. mohor 7925d 22h /ethmac/tags/rel_20
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7926d 18h /ethmac/tags/rel_20
158 Typo fixed. mohor 7926d 18h /ethmac/tags/rel_20
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7928d 23h /ethmac/tags/rel_20
156 Valid testbench. mohor 7928d 23h /ethmac/tags/rel_20
155 Minor changes. mohor 7929d 00h /ethmac/tags/rel_20
154 Design document is still under construction. mohor 7929d 23h /ethmac/tags/rel_20
153 Temp version (backup). mohor 7930d 14h /ethmac/tags/rel_20
152 Version 1.16 created. See revision history in the document for details. mohor 7930d 14h /ethmac/tags/rel_20
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7930d 16h /ethmac/tags/rel_20
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7930d 16h /ethmac/tags/rel_20
148 Bug when last byte of destination address was not checked fixed. mohor 7930d 16h /ethmac/tags/rel_20
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7930d 16h /ethmac/tags/rel_20
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7930d 16h /ethmac/tags/rel_20
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7930d 16h /ethmac/tags/rel_20
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7946d 18h /ethmac/tags/rel_20
141 Syntax error fixed. mohor 7949d 12h /ethmac/tags/rel_20
140 Syntax error fixed. mohor 7949d 12h /ethmac/tags/rel_20
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7949d 12h /ethmac/tags/rel_20
138 Synchronous reset added. mohor 7949d 12h /ethmac/tags/rel_20
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7949d 12h /ethmac/tags/rel_20
136 Parameter ResetValue changed to capital letters. mohor 7949d 22h /ethmac/tags/rel_20
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 7951d 14h /ethmac/tags/rel_20
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7951d 15h /ethmac/tags/rel_20

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.