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162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7899d 11h /ethmac/tags/rel_20/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7899d 17h /ethmac/tags/rel_20/
160 error acknowledge cycle termination added to display. mohor 7899d 17h /ethmac/tags/rel_20/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7900d 13h /ethmac/tags/rel_20/
158 Typo fixed. mohor 7900d 14h /ethmac/tags/rel_20/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7902d 19h /ethmac/tags/rel_20/
156 Valid testbench. mohor 7902d 19h /ethmac/tags/rel_20/
155 Minor changes. mohor 7902d 19h /ethmac/tags/rel_20/
154 Design document is still under construction. mohor 7903d 18h /ethmac/tags/rel_20/
153 Temp version (backup). mohor 7904d 09h /ethmac/tags/rel_20/

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