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224 Signals for a wave window in Modelsim. tadejm 7467d 18h /ethmac/tags/rel_20/
223 Some code changed due to bug fixes. tadejm 7467d 18h /ethmac/tags/rel_20/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7471d 16h /ethmac/tags/rel_20/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7474d 17h /ethmac/tags/rel_20/
218 Typo error fixed. (When using Bist) mohor 7474d 19h /ethmac/tags/rel_20/
217 Bist supported. mohor 7474d 19h /ethmac/tags/rel_20/
216 Bist signals added. mohor 7474d 19h /ethmac/tags/rel_20/
215 Bist supported. mohor 7474d 19h /ethmac/tags/rel_20/
214 Signals for WISHBONE B3 compliant interface added. mohor 7475d 15h /ethmac/tags/rel_20/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7475d 15h /ethmac/tags/rel_20/
212 Minor $display change. mohor 7475d 15h /ethmac/tags/rel_20/
211 Bist added. mohor 7475d 16h /ethmac/tags/rel_20/
210 BIST added. mohor 7475d 16h /ethmac/tags/rel_20/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7476d 19h /ethmac/tags/rel_20/
208 Virtual Silicon RAMs moved to lib directory tadej 7492d 13h /ethmac/tags/rel_20/
207 Virtual Silicon RAM support fixed tadej 7492d 13h /ethmac/tags/rel_20/
206 Virtual Silicon RAM added to the simulation. mohor 7492d 13h /ethmac/tags/rel_20/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7492d 14h /ethmac/tags/rel_20/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7492d 14h /ethmac/tags/rel_20/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7492d 14h /ethmac/tags/rel_20/

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