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[/] [ethmac/] [tags/] [rel_20/] - Rev 227

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Rev Log message Author Age Path
227 Changed BIST scan signals. tadejm 7864d 16h /ethmac/tags/rel_20
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7864d 18h /ethmac/tags/rel_20
225 Some minor changes. tadejm 7864d 18h /ethmac/tags/rel_20
224 Signals for a wave window in Modelsim. tadejm 7864d 19h /ethmac/tags/rel_20
223 Some code changed due to bug fixes. tadejm 7864d 20h /ethmac/tags/rel_20
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7868d 17h /ethmac/tags/rel_20
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7871d 18h /ethmac/tags/rel_20
218 Typo error fixed. (When using Bist) mohor 7871d 20h /ethmac/tags/rel_20
217 Bist supported. mohor 7871d 20h /ethmac/tags/rel_20
216 Bist signals added. mohor 7871d 20h /ethmac/tags/rel_20
215 Bist supported. mohor 7871d 21h /ethmac/tags/rel_20
214 Signals for WISHBONE B3 compliant interface added. mohor 7872d 17h /ethmac/tags/rel_20
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7872d 17h /ethmac/tags/rel_20
212 Minor $display change. mohor 7872d 17h /ethmac/tags/rel_20
211 Bist added. mohor 7872d 17h /ethmac/tags/rel_20
210 BIST added. mohor 7872d 17h /ethmac/tags/rel_20
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7873d 20h /ethmac/tags/rel_20
208 Virtual Silicon RAMs moved to lib directory tadej 7889d 14h /ethmac/tags/rel_20
207 Virtual Silicon RAM support fixed tadej 7889d 14h /ethmac/tags/rel_20
206 Virtual Silicon RAM added to the simulation. mohor 7889d 14h /ethmac/tags/rel_20

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