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Rev Log message Author Age Path
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7381d 01h /ethmac/tags/rel_20/
243 Late collision is not reported any more. tadejm 7381d 06h /ethmac/tags/rel_20/
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7381d 21h /ethmac/tags/rel_20/
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7381d 21h /ethmac/tags/rel_20/
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7381d 21h /ethmac/tags/rel_20/
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7381d 21h /ethmac/tags/rel_20/
238 Defines fixed to use generic RAM by default. mohor 7394d 01h /ethmac/tags/rel_20/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7396d 06h /ethmac/tags/rel_20/
235 rev 4. mohor 7396d 21h /ethmac/tags/rel_20/
234 Figure list assed to the revision 3. mohor 7397d 05h /ethmac/tags/rel_20/
233 Revision 0.3 released. Some figures added. mohor 7397d 05h /ethmac/tags/rel_20/
232 fpga define added. mohor 7402d 00h /ethmac/tags/rel_20/
231 Description of Core Modules added (figure). mohor 7404d 02h /ethmac/tags/rel_20/
229 case changed to casex. mohor 7407d 22h /ethmac/tags/rel_20/
227 Changed BIST scan signals. tadejm 7408d 02h /ethmac/tags/rel_20/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7408d 04h /ethmac/tags/rel_20/
225 Some minor changes. tadejm 7408d 04h /ethmac/tags/rel_20/
224 Signals for a wave window in Modelsim. tadejm 7408d 05h /ethmac/tags/rel_20/
223 Some code changed due to bug fixes. tadejm 7408d 05h /ethmac/tags/rel_20/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7412d 03h /ethmac/tags/rel_20/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7415d 04h /ethmac/tags/rel_20/
218 Typo error fixed. (When using Bist) mohor 7415d 06h /ethmac/tags/rel_20/
217 Bist supported. mohor 7415d 06h /ethmac/tags/rel_20/
216 Bist signals added. mohor 7415d 06h /ethmac/tags/rel_20/
215 Bist supported. mohor 7415d 07h /ethmac/tags/rel_20/
214 Signals for WISHBONE B3 compliant interface added. mohor 7416d 02h /ethmac/tags/rel_20/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7416d 02h /ethmac/tags/rel_20/
212 Minor $display change. mohor 7416d 03h /ethmac/tags/rel_20/
211 Bist added. mohor 7416d 03h /ethmac/tags/rel_20/
210 BIST added. mohor 7416d 03h /ethmac/tags/rel_20/

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