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[/] [ethmac/] [tags/] [rel_20/] - Rev 266

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266 Flow control test almost finished. mohor 7833d 20h /ethmac/tags/rel_20
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7834d 00h /ethmac/tags/rel_20
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7834d 11h /ethmac/tags/rel_20
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7834d 11h /ethmac/tags/rel_20
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7834d 11h /ethmac/tags/rel_20
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7834d 23h /ethmac/tags/rel_20
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7835d 12h /ethmac/tags/rel_20
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7835d 13h /ethmac/tags/rel_20
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7835d 13h /ethmac/tags/rel_20
255 TPauseRq synchronized to tx_clk. mohor 7835d 13h /ethmac/tags/rel_20
254 Temp version. mohor 7836d 17h /ethmac/tags/rel_20
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7836d 19h /ethmac/tags/rel_20
252 Just some updates. tadejm 7836d 19h /ethmac/tags/rel_20
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7836d 19h /ethmac/tags/rel_20
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7836d 19h /ethmac/tags/rel_20
248 wb_rst_i is used for MIIM reset. mohor 7837d 20h /ethmac/tags/rel_20
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7840d 23h /ethmac/tags/rel_20
245 Rev 1.7. mohor 7841d 16h /ethmac/tags/rel_20
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7841d 18h /ethmac/tags/rel_20
243 Late collision is not reported any more. tadejm 7842d 00h /ethmac/tags/rel_20
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7842d 15h /ethmac/tags/rel_20
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7842d 15h /ethmac/tags/rel_20
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7842d 15h /ethmac/tags/rel_20
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7842d 15h /ethmac/tags/rel_20
238 Defines fixed to use generic RAM by default. mohor 7854d 19h /ethmac/tags/rel_20
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7857d 00h /ethmac/tags/rel_20
235 rev 4. mohor 7857d 15h /ethmac/tags/rel_20
234 Figure list assed to the revision 3. mohor 7857d 23h /ethmac/tags/rel_20
233 Revision 0.3 released. Some figures added. mohor 7857d 23h /ethmac/tags/rel_20
232 fpga define added. mohor 7862d 18h /ethmac/tags/rel_20

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