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29 Generic memory model is used. Defines are changed for the same reason. mohor 8225d 18h /ethmac/tags/rel_20/
28 New release. Name changed to lower case. mohor 8228d 09h /ethmac/tags/rel_20/
27 File names changed to lower case. mohor 8228d 10h /ethmac/tags/rel_20/
26 First release of product brief. mohor 8228d 10h /ethmac/tags/rel_20/
25 First release of product brief. mohor 8228d 10h /ethmac/tags/rel_20/
24 Log file added. mohor 8250d 21h /ethmac/tags/rel_20/
23 Number of addresses (wb_adr_i) minimized. mohor 8250d 21h /ethmac/tags/rel_20/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8251d 00h /ethmac/tags/rel_20/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8251d 20h /ethmac/tags/rel_20/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8275d 17h /ethmac/tags/rel_20/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8275d 18h /ethmac/tags/rel_20/
18 Few little NCSIM warnings fixed. mohor 8288d 18h /ethmac/tags/rel_20/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8315d 18h /ethmac/tags/rel_20/
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8323d 00h /ethmac/tags/rel_20/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8324d 18h /ethmac/tags/rel_20/
14 Unconnected signals are now connected. mohor 8328d 23h /ethmac/tags/rel_20/
13 New directory structure. Files upodated and put together. mohor 8331d 08h /ethmac/tags/rel_20/
12 Directory structure changed. Files checked and joind together. mohor 8331d 11h /ethmac/tags/rel_20/
11 Directory structure changed. Files checked and joind together. mohor 8331d 11h /ethmac/tags/rel_20/
10 Directory structure changed. Files checked and joind together. mohor 8331d 11h /ethmac/tags/rel_20/
9 Documentation updated to be synchronized to the verilog files. mohor 8358d 20h /ethmac/tags/rel_20/
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8386d 00h /ethmac/tags/rel_20/
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8386d 00h /ethmac/tags/rel_20/
6 no message mohor 8386d 01h /ethmac/tags/rel_20/
5 This is a Microsoft version of the spec in the pdf format. mohor 8390d 10h /ethmac/tags/rel_20/
4 deleted mohor 8390d 10h /ethmac/tags/rel_20/
2 no message mohor 8462d 10h /ethmac/tags/rel_20/
1 Standard project directories initialized by cvs2svn. 8462d 10h /ethmac/tags/rel_20/

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