OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] - Rev 35

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8191d 02h /ethmac/tags/rel_20
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8191d 02h /ethmac/tags/rel_20
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8191d 07h /ethmac/tags/rel_20
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8191d 07h /ethmac/tags/rel_20
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8191d 08h /ethmac/tags/rel_20
30 BD section updated. mohor 8193d 04h /ethmac/tags/rel_20
29 Generic memory model is used. Defines are changed for the same reason. mohor 8213d 03h /ethmac/tags/rel_20
28 New release. Name changed to lower case. mohor 8215d 19h /ethmac/tags/rel_20
27 File names changed to lower case. mohor 8215d 19h /ethmac/tags/rel_20
26 First release of product brief. mohor 8215d 19h /ethmac/tags/rel_20
25 First release of product brief. mohor 8215d 19h /ethmac/tags/rel_20
24 Log file added. mohor 8238d 06h /ethmac/tags/rel_20
23 Number of addresses (wb_adr_i) minimized. mohor 8238d 06h /ethmac/tags/rel_20
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8238d 09h /ethmac/tags/rel_20
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8239d 05h /ethmac/tags/rel_20
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8263d 02h /ethmac/tags/rel_20
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8263d 03h /ethmac/tags/rel_20
18 Few little NCSIM warnings fixed. mohor 8276d 03h /ethmac/tags/rel_20
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8303d 03h /ethmac/tags/rel_20
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8310d 09h /ethmac/tags/rel_20

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.