OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [rtl/] - Rev 212

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 Minor $display change. mohor 7874d 04h /ethmac/tags/rel_20/rtl
211 Bist added. mohor 7874d 04h /ethmac/tags/rel_20/rtl
210 BIST added. mohor 7874d 04h /ethmac/tags/rel_20/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7891d 03h /ethmac/tags/rel_20/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7891d 03h /ethmac/tags/rel_20/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7894d 04h /ethmac/tags/rel_20/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7902d 06h /ethmac/tags/rel_20/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7903d 07h /ethmac/tags/rel_20/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7904d 07h /ethmac/tags/rel_20/rtl
165 HASH improvement needed. mohor 7904d 10h /ethmac/tags/rel_20/rtl
164 Ethernet debug registers removed. mohor 7904d 10h /ethmac/tags/rel_20/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7905d 08h /ethmac/tags/rel_20/rtl
160 error acknowledge cycle termination added to display. mohor 7905d 08h /ethmac/tags/rel_20/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7906d 04h /ethmac/tags/rel_20/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7910d 02h /ethmac/tags/rel_20/rtl
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 7910d 02h /ethmac/tags/rel_20/rtl
148 Bug when last byte of destination address was not checked fixed. mohor 7910d 02h /ethmac/tags/rel_20/rtl
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7910d 02h /ethmac/tags/rel_20/rtl
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7910d 02h /ethmac/tags/rel_20/rtl
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7910d 02h /ethmac/tags/rel_20/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.